`include "defines.v"

module wb_stage(
    input wire [`RAM_ADDR_WIDTH - 1 : 0]    inst_addr_i,
    input wire [`INST_WIDTH - 1: 0]         inst_i,

    input wire                              rd_w_ena_i,
    input wire [4 : 0]                      rd_w_addr_i,
    input wire [`REG_BUS]                   rd_w_data_i,

    input wire                              csr_w_ena_i,
    input wire [11: 0]                      csr_w_addr_i,
    input wire [`REG_BUS]                   csr_w_data_i,

    input wire [`REG_BUS]                   exception_type_i,
    input wire                              valid_i,

    input wire                              skip_i,

    output wire [`RAM_ADDR_WIDTH - 1 : 0]   inst_addr_o,
    output wire [`INST_WIDTH - 1: 0]        inst_o,

    output wire                             rd_w_ena_o,
    output wire [4 : 0]                     rd_w_addr_o,
    output wire [`REG_BUS]                  rd_w_data_o,

    output wire                             csr_w_ena_o,
    output wire [11: 0]                     csr_w_addr_o,
    output wire [`REG_BUS]                  csr_w_data_o,

    output wire [`REG_BUS]                  exception_type_o,
    output wire                             valid_o,

    output wire                             skip_o
);
    assign inst_addr_o = inst_addr_i;
    assign inst_o      = inst_i;

    assign rd_w_ena_o  = exception_type_i == `ZERO_WORD ? rd_w_ena_i : 1'b0;
    assign rd_w_addr_o = rd_w_addr_i;
    assign rd_w_data_o = rd_w_data_i;

    assign csr_w_ena_o = exception_type_i == `ZERO_WORD ? csr_w_ena_i : 1'b0;
    assign csr_w_addr_o= csr_w_addr_i;
    assign csr_w_data_o= csr_w_data_i;

    assign exception_type_o = exception_type_i;

    assign valid_o = exception_type_i[39] == 1'b0 && exception_type_i[5] == 1'b0 ? valid_i : 1'b0;
    assign skip_o  = inst_i == 32'h7b ? 1'b1 : skip_i;
endmodule
